View CY2SSTU877_647457.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CY2SSTU877
1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Features
* Operating frequency: 125 MHz to 500 MHz * Supports DDRII SDRAM * Ten differential outputs from one differential input * Spread-Spectrum-compatible * Low jitter (cycle-to-cycle): < 40 ps * Very low skew: < 40 ps * Power management control input * 1.8V operation * Fully JEDEC-compliant * 52-ball BGA and a 40-pin MLF (QFN) This phase-locked loop (PLL) clock buffer is designed for a VDD of 1.8V, an AVDD of 1.8V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF (QFN). The device is a zero delay buffer that distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT#). The input clocks (CK, CK#), the feedback clocks (FBIN, FBIN#), the LVCMOS (OE, OS), and the analog power input (AVDD) control the clock outputs. The PLL in the CY2SSTU877 clock driver uses the input clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CK, CK#) are logic low, the device will enter a low-power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low-power state where all outputs, the feedback, and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FBIN, FBIN#) and the input clock pair (CK, CK#) within the specified stabilization time tL.
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTU877 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTU877 features differential feedback clock outputs and inputs. This allows the CY2SSTU877 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTU877 locks onto the input reference and translates with near zero delay to low-skew outputs.
Block Diagram
Pin Configuration
52 BGA
1 A B C D E F G H J K
Y1 Y1# Y2# Y2 CK CK# AGND AVDD Y3 Y3#
2
Y0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND Y4#
Y1#
3
Y0# GND NB VDDQ NB NB VDDQ NB GND Y4
VDDQ Y0# Y5#
4
Y5# GND NB VDDQ NB NB VDDQ NB GND Y9
5
Y5 GND GND OS VDDQ OE VDDQ GND GND Y5#
VDDQ Y6#
6
Y6 Y6# Y7# Y7 FBIN FBIN# FBOUT# FBOUT Y8 Y8#
Y1
Y0
Y5
VD DQ Y2# Y2 C LK C LK # VD DQ AG N D A VD D VD DQ GND
1 2 3 4 5 6 7 8 9
40 39 38
37 36
35
Y6
34
33 32
31
30 29 28
Y7# Y7 VD D Q FB IN FB IN # FB O U T# FB O U T VD D Q OE OS
40 Q FN C Y 2S S T U 877
27 26 25 24 23 22
10 11 12 13
14 15
16
17
18 19 20 21
Y3#
Y4#
Y9#
VDDQ
Y8#
Cypress Semiconductor Corporation Document #: 38-07575 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 19, 2005
VDDQ
Y3
Y4
Y9
Y8
PRELIMINARY
Pin Description
Pin No. (BGA) G1 H1 E1, F1 E6, F6 H6, G6 7 8 4, 5 27, 26 24, 25 QFN AGND AVDD CLK, CLK# FBIN, FBIN# FBOUT, FBOUT# GND Name 1.8V analog supply Description Ground for 1.8V analog supply
CY2SSTU877
Differential clock input with a (10K-100K) pull-down resistor Feedback differential clock input Feedback differential clock output Ground
B2, B3, B4, B5, C2, 10 C5, H2, H5, J2, J3, J4, J5 F5 D5 22 21
OE OS
Output enable (ASYNC) for Y[0:9] and Y# [0:9] Output Select (Tied to GND or VCC) 1.8V supply Buffered output of input clock, CLK Buffered output of input clock, CLK
D2, D3, D4, E2, E5, 1, 6, 9, 15, 20, 23, 28, VDDQ F2, G2, G3, G4, G5 31, 36 A2, A1, D1, J1, K3, A5, A6, D6, J6, K4, 38, 39, 3, 11, 14, 34, Y [0:9] 33, 29, 19, 16
A3, B1, C1, K1, K2, 37, 40, 2, 12, 13, 35, Y# [0:9] A4, B6, C6, K6, K5 32, 30, 18, 17 Table 1. Function Table Inputs AVDD GND GND GND GND VDD VDD VDD VDD VDD X OE H H L L L L H H X X OS X X H L H L X X X X CLK L H L H L H L H L H CLK# H L H L H L H L L H Y L H Lz
Outputs Y# H L Lz Lz,Y7# Active Lz Lz,Y7# Active H L Lz FBOUT L H L H L H L H Lz Reserved FBOUT# H L H L H L H L Lz PLL Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off On On On On Off
Lz,Y7 Active Lz Lz,Y7 Active L H Lz
Recommended Operating Conditions
Parameter TA (Ind.) TA (Com.) VDD Description Ambient Operating Temp Ambient Operating Temp Operating Voltage Condition Min. -40 0 1.7 Max. 85 70 1.9 Unit C C V
Document #: 38-07575 Rev. *B
Page 2 of 9
PRELIMINARY
Absolute Maximum Conditions
Parameter VIN VOUT TS VCC IIK IOK IO Description Input Voltage Range Output Voltage Range Storage Temperature Supply Voltage Range Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through VDD/GND Condition Min. -0.5 -0.5 -65 -0.5 -50 -50 -50 -100
CY2SSTU877
Max. VDDQ + 0.5 VDDQ + 0.5 150 2.5 50 50 50 100 Unit V V C V mA mA mA mA
DC Electrical Specifications
Parameter VIX VID DC VID AC VIL VIH VOL VOH IOH IOL VIK VOD VOX Description Input Differential Crossing Voltage Input Differential Voltage (DC Values) Input Differential Voltage (AC Values) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Current Output Low Current Input Clamping Voltage Output Differential Voltage Output Differential Crossing Voltage II = -18 mA 0.5 VDDQ/2 - 0.08 VDDQ/2 + 0.08 (OE, OS, CK, CK#) (OE, OS, CK, CK#) IOL = 100 A IOL = 9 mA IOH = -100 A IOH = -9 mA VDDQ - 0.2 1.1 -9 9 -1.2 0.65 * VDDQ 0.1 0.6 Conditions Min. (VDDQ/2) - 0.15 0.3 0.6 Max. (VDDQ/2) + 0.15 VDDQ + 0.4 VDDQ + 0.4 0.35 * VDDQ Unit V V V V V V V V V mA mA V V V
AC Electrical Specifications
Parameter SLR(O) SLR(I) CIN COUT CIN(DELTA) Description Output Slew Rate Input Slew Rate Input Capacitance Conditions Y[0:9], Y#[0:9], FBOUT, FBOUT# CLK, CLK#, FBIN, FBIN# OE (Input Capacitance of CK, CK#, FBIN, FBIN#) Vi = VDDQ or GND Ci(delta) (CK, CK#, FBIN, FBIN#) Vi = VDDQ or GND Min. 1.5 1 0.5 2 3 Max. 3 4 Unit V/ns V/ns V/ns pF pF -0.25 0.25 pF
AC Timing Specifications
Parameter FCLK TDC TLOCK Tjitt (cc) Tjit (Period) Duty Cycle PLL Lock Time Cycle-to-cycle jitter Period Cycle-to-cycle jitter Description Clock Frequency Conditions Min. 125 40 - -30 -40 Max. 500 60 10 30 20 Unit MHz % s ps ps
Document #: 38-07575 Rev. *B
Page 3 of 9
PRELIMINARY
AC Timing Specifications (continued)
Parameter Tjit (H-Period) Td(0) Td(0) TSKEW TR/TF TODC TOENB TODIS TPLH Description Half Period Cycle-to-cycle jitter Static Phase Offset Dynamic Phase Offset Clock Skew Rise/Fall Time Output Duty Cycle Output Enable Time Output Disable Time Propagation Delay OE to any Y/Y# OE to any Y/Y# (Y[0:9], Y#[0:9] @ 500 MHz) Conditions Above 270 MHz Below 270 MHz Average 1000 cycles Min. -45 -70 -50 -30 - - 49 - -
CY2SSTU877
Max. 45 70 50 30 25 300 51 8 8 8 Unit ps ps ps ps ps ps % ns ns ns
Figure 1. Test Loads for Timing Measurement #1
Figure 2. Test Loads for Timing Measurement #2
Document #: 38-07575 Rev. *B
Page 4 of 9
PRELIMINARY
CY2SSTU877
Figure 3. Cycle to Cycle Jitter
Figure 4. Period Jitter
Figure 5. Half Period Jitter
Document #: 38-07575 Rev. *B
Page 5 of 9
PRELIMINARY
CY2SSTU877
Figure 6. Static Phase Offset
Figure 7. Dynamic Phase Offset
Figure 8. Output Skew
Document #: 38-07575 Rev. *B
Page 6 of 9
PRELIMINARY
CY2SSTU877
Figure 9. Time Delay Between OE and Clock Output (Y, Y)
Figure 10. Input/Output Slew Rates
Ordering Information
Part Number Standard CY2SSTU877LFC-XX CY2SSTU877LFC-XXT CY2SSTU877BVC-XX CY2SSTU877BVC-XXT CY2SSTU877LFI-XX CY2SSTU877LFI-XXT CY2SSTU877BVI-XX CY2SSTU877BVI-XXT Lead-free CY2SSTU877LFXC-XX CY2SSTU877LFXC-XXT CY2SSTU877BVXC-XX CY2SSTU877BVXC-XXT CY2SSTU877LFXI-XX CY2SSTU877LFXI-XXT CY2SSTU877BVXI-XX CY2SSTU877BVXI-XXT 40-pin QFN 40-pin QFN - Tape and Reel 52-pin VFBGA 52-pin VFBGA- Tape and Reel 40-pin QFN 40-pin QFN - Tape and Reel 52-pin VFBGA 52-pin VFBGA- Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70CC Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C 40-pin QFN 40-pin QFN - Tape and Reel 52-pin VFBGA 52-pin VFBGA- Tape and Reel 40-pin QFN 40-pin QFN - Tape and Reel 52-pin VFBGA 52-pin VFBGA- Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70CC Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Package Type Product Flow
Document #: 38-07575 Rev. *B
Page 7 of 9
PRELIMINARY
Package Drawing
TOP VIEW
CY2SSTU877
52 VFBGA 4.5 x 7.0 x 1.0 MM BV52A
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER 1 A B C 0.65 D 7.000.10 7.000.10 5.85 E F G H J K 2 3 4 5 6
O0.300.05(52X)
6
5
4
3
2
1 A B C D E F G H J K
2.925
A B 4.500.10
A
1.625 0.65 3.25 B 4.500.10
0.55 MAX.
0.25 C
0.210.05
0.15(4X) 0.15 C
SEATING PLANE 0.26 MAX. C 1.00 MAX
DIMENSION IN MM REFERENCE JEDEC MO-225
51-85192-**
40-lead QFN 6 x 6 MM LF40A
TOP VIEW SIDE VIEW BOTTOM VIEW
0.08[0.003] A 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] N 1 0.60[0.024] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF.
C
0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
0.30[0.012] 0.50[0.020]
(PAD SIZE VARY BY DEVICE TYPE)
0-12
0.50[0.020] C 4.45[0.175] 4.55[0.179]
0.24[0.009] 0.60[0.024]
(4X)
SEATING PLANE
51-85190-**
All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07575 Rev. *B Page 8 of 9
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
4.45[0.175] 4.55[0.179]
E-PAD
PRELIMINARY
Document History Page
Document Title:CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Document Number: 38-07575 Rev. ** *A *B ECN No. 129198 204389 310414 Issue Date 08/22/03 See ECN See ECN Orig. of Change RGL RGL RGL New Data Sheet Description of Change
CY2SSTU877
Added more Information. Deleted 4 rows from the bottom of the Pin description. Changed Advance Info. to Preliminary status Added Lead-free devices
Document #: 38-07575 Rev. *B
Page 9 of 9

▲Up To Search▲

Price & Availability of CY2SSTU877

	To Download CY2SSTU877 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .